Job Closed
Design Verification Engineer
- Source: Ashby
- Normal Computing
- $140,000 to $180,000 /yr
- On-site
- New York City
- Full-Time
- Mid level
Job Description
- As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs on the road to tapeout, and set the quality bar for what our AI learns: reviewing generated verification collateral and shaping the standards our models train against
- From time to time, you may also be tapped to support a customer deployment alongside our forward-deployed team, where your verification credibility helps our AI platform land inside real DV flows
- The through-line is your DV expertise, applied to silicon that computes differently than anything you’ve verified before, and to the AI that is changing how verification gets done
- This is a seat for a verification engineer who wants their craft to compound rather than repeat
- Thermodynamic ASIC Verification: Own design verification for Normal’s internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure, supporting the program to tapeout
- AI Product Refinement: Review AI-generated verification collateral to shape product strategy and tool usability in collaboration with the ML and product teams
- Data Quality Bar: Set the quality standard for verification training data: define rubrics, curate golden examples, and partner with our Data team, who own the pipelines, so our models learn from verification artifacts a real DV engineer would sign off on
- Deployment Support: When needed, support customer engagements alongside our forward-deployed team: validating AI-generated collateral against real customer specifications and lending DV credibility to deployments
- Tooling: Set up and evaluate EDA tools, ensuring usability and effective deployment on shared computing resources internally and in customer environments- Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction
- Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting
- Willingness to occasionally support customer-facing deployment work, including some travel
- Excellent written and spoken communication skills: you can hold the room with a customer’s verification lead as credibly as you hold a debug session
- 5+ years of experience in digital verification at a major semiconductor or EDA tool company
- Hands-on use of LLMs or agentic tools in verification workflows
- Experience in a customer-facing, field-application, or forward-deployed engineering role at a semiconductor or EDA company
- Exposure to analog, mixed-signal, or unconventional compute verification
Skills
- Stimulus
- Python
- perl
- ashby
This job is no longer accepting applications.
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