Job Closed
FPGA Design Engineer
- Source: Ashby
- Normal Computing
- $200,000 to $280,000 /yr
- On-site
- New York City
- Full-Time
- Mid level
Job Description
- Validating conventional silicon is a solved discipline. Validating silicon that computes with noise is not, and you will be the one who figures out how
- As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization
- Your scope spans the entire FPGA lifecycle: selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams
- FPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development
- RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs
- IP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers)
- High-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers
- Post-Silicon Validation: Build FPGA-based “tester” designs for silicon bring-up, device characterization, and automated test environments
- Hardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows
- Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links- Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog)
- Strong Python for automation, test, and build tooling
- Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces
- Strong board-level bring-up and lab debugging skills on real hardware
- Startup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics
- Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment
- CI/CD for hardware (GitLab CI, Docker-based build and test)
- SERDES tuning and signal integrity fundamentals
- Mixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute
- Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines
- Verification frameworks like Cocotb, UVM, or OSVVM
Skills
- amd
- Python
- cplusplus
- gitlab
- gitlab-ci
- Docker
- ashby
This job is no longer accepting applications.
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