DFT design / methodology development Engineer

Location: Albany (NY)–preferred, Santa Clara (CA), or Tokyo (Japan)

Role Overview:

• You will be responsible for the Design for Test (DFT) strategy within the 2nm reference flow. This role involves integrating advanced
• Scan and MBIST tools to ensure high testability for complex GAA designs. You will also lead the evaluation and adoption of
• next-generation DFT methodologies to address the challenges of ultra-fine process nodes.

About Rapidus

Rapidus Corporation, founded in 2022, is Japan-led initiative to build a world-class advanced logic semiconductor foundry. With a bold vision to accelerate innovation, we are pioneering cutting-edge logic semiconductor research, development, design, and manufacturing to transform the global semiconductor industry.

Why Join Us

You will play a central leadership role in building the world’s most advanced 2nm and next‑generation enablement ecosystem , shaping the foundation for future semiconductor innovation.

You will focus on the implementation stages (Synthesis and PnR) of the digital reference flow. Additionally, you will lead the adoption of next-generation automation tools, including AI/ML-driven DSE (Design space exploration)

Key Responsibilities:

• Integrate Scan and MBIST (Memory Built-In Self-Test) tools into the digital reference flow.
• Evaluate and implement advanced DFT technologies, such as Streaming Scan Network (SSN), to optimize test data volume and test time.
• Develop and validate ATPG (Automatic Test Pattern Generation) methodologies utilizing cell-aware (intra-cell) fault models to achieve high defect coverage at the 2nm node.
• Conduct evaluation and feasibility studies for new failure analysis methodologies to improve yield ramp-up.
• Work closely with EDA vendors to implement these advanced DFT features and collaborate with design partners for pattern generation and silicon-based failure diagnosis.
• Support DFT implementation and pattern execution for internal Rapidus test chips.
• Provide customers with comprehensive DFT guidelines and technical support.

Qualifications:

• Solid understanding of DFT methodologies (Scan, MBIST, ATPG).
• Experience with advanced process nodes (7nm FinFET and beyond) is preferred but not mandatory.
• Familiarity with advanced DFT architectures (e.g., SSN, packetized test) and cell-aware testing is highly desirable.
• Proven ability to collaborate with external stakeholders, including EDA vendors and design service partners.

• Collaboration: Proven ability to work effectively with external stakeholders, including EDA vendors and design service partners.

• Education: BS/MS/PhD in Electrical Engineering or a related technical field.

Language: Professional proficiency in English (Japanese skills are a plus).

Benefits

• Comprehensive Health, Dental and Vision coverage, fully at company’s expense (no deductibles)
• 401k with no employer match