PLL IC Design Engineer - TeraWave

Application Close Date Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.

We are seeking an IC Design Engineer to work on the development of integrated Phase-Locked Loops (PLLs) and clocking systems in advanced CMOS/SiGe processes. This role is essential for advancing our technology offerings in space communication systems. You will be responsible for delivering state-of-the-art performance while contributing to innovative solutions that drive Blue Origin’s mission of enabling millions to live and work in space for the benefit of Earth.

Special Mentions

• Relocation provided
• Travel expected up to 10% of the time
• Interviews will include a technical assessment
• This role will be based onsite in San Diego, CA; Bay Area, CA; or Renton, WA. A temporary remote work exception is approved while our Bay Area and San Diego sites are being developed.

Responsibilities Include But Are Not Limited To

• Owning the system and circuit design of PLLs and clock distribution circuits in advanced CMOS technologies, focusing on performance optimization and trade-off analysis (phase noise / jitter, power, etc.).
• Utilizing full proficiency in Spectre and AMS flows to develop high-performance PLL circuits.
• Collaborating with RF and SOC system architects and chip leads to define requirements for PLLs and their sub-blocks based on system specifications.
• Overseeing layout, top-level integration, floorplanning, and verification of the overall design for successful tape-out cycle.
• Working closely with validation and product engineers to develop test plans, facilitate bring-up, optimize performance, and ensure reliable & high-yield production cycles.
• Investigating and implementing fundamental analog building blocks to enhance overall circuit performance
• Mentoring junior engineers for best design practices in analog domain.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, or related technical discipline
• 7+ years of experience in the design and development of fractional-N PLLs, DLLs, and their sub-circuits in FinFET CMOS nodes such as 7n or more advanced.
• Extensive experience in the design of PLL building blocks such as VCOs, high-speed integer and frac-N pre-scalers, PFDs, charge-pumps, etc.
• Experience with clock domain synchronization techniques within systems involving multiple PLLs and/or clock domains.
• Experience with clock distribution circuit design techniques and optimization, including clock trees, frequency multipliers and dividers, CML buffers, inductive peaking, etc.
• Full proficiency in mixed-mode modeling, simulation, and verification methodologies using toolsets such as MATLAB, Spectre, SystemVerilog, and AMS.
• Extensive experience in PLL silicon characterization and debugging.
• Proficiency in the design of fundamental analog/RF building blocks, including amplifiers, filters, clock buffers, and bias generators.
• Must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Preferred Qualifications

• Advanced degree (MS/PhD) in Electrical Engineering related technical discipline
• Strong expertise in loop design for phase noise/jitter, spur profile, area, and power optimization.
• Experience designing All-Digital PLLs (ADPLL) and or sub-sampling PLLs is a plus.
• Experience with fundamental analog building blocks such as LDOs, and operational amplifiers.
• Fundamental understanding of device physics for process selection and performance optimization.
• Familiarity with digital design, digital verification, and SystemVerilog modeling.

Base Pay Range For CA applicants is …