Design Verification IP Engineer

Design Verification IP Engineer

Location: Remote

Client Microsoft/ HCL

Need W2

Only USC & GC

Job Description:

Responsible for IP/Block-level verification through developing reusable verification environments, executing verification plans, debugging, and coverage closure.

Key Responsibilities

1. Develop and enhance UVM-based testbenches, agents, scoreboards, and assertions.

2. Develop and execute comprehensive verification plans, testcases, and coverage models.

3. Create and execute directed and constrained-random test scenarios for IP verification.

4. Integrate and configure UVCs/VIPs and drive functional and code coverage closure.

5. Verify RTL functionality of IP blocks including FSMs, DAC control logic, and pattern memory/controller modules.

6. Debug RTL, protocol, and verification environment issues.

7. RAL Modeling and Verification

8. Collaborate with RTL and SoC teams to deliver high-quality, reusable verification collateral.

Skill Requirements

1. Strong SystemVerilog and UVM programming experience.

2. Hands-on expertise in IP/Block-level verification and testbench development.

3. Strong understanding of digital design fundamentals, FSM architectures, and RTL verification.

4. Hands-on experience in RAL modeling and RAL-based register verification, including register access, prediction, mirroring, and coverage.

5. Experience with protocol verification, assertions, coverage analysis, and regression management.

6.Familiarity with low-power verification concepts and GLS debug.

7.Strong analytical, debugging, and problem-solving skills.

Thanks & Regards,

Vinay Rama Sesha

[email protected]

+1 732-807-0584

+91 9059962085 Whats App Number